As is well known, the data storage devices using NAND-based flash memories are widely used in a variety of electronic devices. For example, a SD card or a solid state drive (SSD) is a data storage device that uses a NAND-based flash memory to store data. Due to light weight, impact resistance, low power consumption and other benefits, the large-capacity solid state storage device has gradually replaced the conventional hard disc storage device.
FIG. 1 is a schematic functional block diagram illustrating the architecture of a conventional solid state storage device. As shown in FIG. 1, the solid state storage device 100 comprises a control chip 102, a regulator 104, and plural flash memory modules 111˜11N. Generally, as the capacity of the solid state storage device 100 is increased, the number of the flash memory modules is increased.
The solid state storage device 100 is in communication with a host such as a computer host (not shown). According to a control signal, the data of the solid state storage device 100 is accessed by the host. For example, the control signal comprises a command signal, an address signal, a data signal, and so on. Moreover, according to a power signal (e.g. 5V), the host provides power to the solid state storage device 100.
In a normal operation mode, the data of the solid state storage device 100 can be read by the host. According to a read command signal and an address signal of the control signal, the data of a corresponding flash memory module is read by the control chip 102. Then, the data is converted into a data signal by the control chip 102 and transmitted to the host. Moreover, for writing a data from the host into the solid state storage device 100, the data is written into the corresponding flash memory module by the control chip 102 according to a write command signal, an address signal and a data signal of the control signal.
Moreover, the host may provide the power signal to the regulator 104 of the solid state storage device 100. Consequently, the regulator 104 may produce various voltages for powering all components of the solid state storage device 100. For example, the regulator 104 may provide a first supply voltage Vp1 to the control chip 102 and provide a second supply voltage Vp2 to the flash memory modules 111˜11N in order to maintain the normal operation mode of the solid state storage device 100.
Generally, for reducing power consumption, most hosts may be operated in a sleep mode. In the sleep mode, most of circuits in the host are not powered on. Until the user wakes up the host, all circuits of the host are powered on again, and the host enters the normal operation mode again.
In the sleep mode of the host, the host may still provide the power signal to the peripheral device. Moreover, according to a device sleep signal DEVSLP of the control signal, the peripheral device is controlled to be in the sleep mode.
However, for some kinds of solid state storage devices 100, the control chip 102 is unable to support the sleep mode. That is, the device sleep signal DEVSLP fails to be received by the control chip 102. Under this circumstance, if the host is in the sleep mode, in response to the device sleep signal DEVSLP, the solid state storage device 100 cannot enter the sleep mode under the control of the control chip 102.
Meanwhile, the control chip 102 and the flash memory modules 111˜11N are still powered on by the first supply voltage Vp1 and the second supply voltage Vp2 from the regulator 104. In other words, when the host is in the sleep mode, the conventional solid state storage device 100 is only maintained in an idle mode. In the idle mode, the power consumption of the conventional solid state storage device 100 is still high.